View ML6401CS-3_1280412.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

March 1997
ML6401* 8-Bit 20 MSPS A/D Converter
GENERAL DESCRIPTION
The ML6401 is a single-chip 8-bit 20 MSPS BiCMOS Video A/D Converter IC, incorporating a differential input track and hold, clock generation circuitry, and reference voltage. The input track and hold consists of a low (4pF) capacitance input and a fast settling operational amplifier. The A/D conversion is accomplished through a pipeline approach, reducing the number of required comparators and latches. The non-over-lapping clocks required for this architecture are all internally generated. Clock generation circuitry requires only one 50% duty cycle clock input. The use of error correction throughout the A/D converter improves DNL. All bias voltages and currents required by the A/D converter are internally generated. The digital outputs are three-stateable.
FEATURES
s 5.0V 10% single supply operation s Internal reference voltage s Power dissipation less than 200mW typical s Replaces TMC1175MC20 and AD775JR, functionally compatible to Sony CXD1175AM/AP s 16-pin reduced pin count packages available: ML6401CS-3 s Low input capacitance track and hold: 4pF s Onboard non-overlapping clock generation to minimize external components s Three-state outputs and no missing codes s 150MHz input track and hold
BLOCK DIAGRAM/TYPICAL APPLICATION
5V VIDEO INPUT + 47F VIN- 0.1F ADC 2 1k 1k SUB DAC AMP 10F + VIN+ 150MHz T&H ADC 1
*Some Packages Are End Of Life
VDDA
VDDA
VDDA
VDDD
VDDD OE D7 D6 D5
75
SUB DAC AMP
ADC 3
DIGITAL ERROR CORRECTION
D4 D3
VIN-BIAS 1.5V VREFOUT VREFIN INTERNAL 1.0V REFERENCES CLOCK GENERATOR D0 D2 D1
GNDA
GNDA
CLK
GNDD
GNDO
20MHz
1
ML6401
PIN CONFIGURATION
ML6401-1 24-Pin SOIC (S24W)
OE GNDO D0 D1 D2 D3 D4 D5 D6 D7 VDDO CLK
1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13
ML6401-3 16-Pin SOIC (S16N)
GNDD VIN- VIN-BIAS GNDA GNDA VIN+ VDDA VREFIN VREFOUT VDDA VDDA VDDD TOP VIEW D0 D1 D2 D3 D4 D5 D6 D7
1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9
OE GNDD GNDA VIN+ VDDA VDDD CLK VDDD
TOP VIEW
PIN DESCRIPTION (Pin numbers in parentheses are for S16N package)
PIN 1 (16) 2 3 4 5 6 7 8 9 (1) (2) (3) (4) (5) (6) (7) NAME OE GNDO D0 D1 D2 D3 D4 D5 D6 D7 VDDO CLK DESCRIPTION Output Enable. A logic low signal on this pin enables the outputs. Output ground pin. D0 (LSB) output signal (TTL compatible). D1 output signal (TTL compatible). D2 output signal (TTL compatible). D3 output signal (TTL compatible). D4 output signal (TTL compatible). D5 output signal (TTL compatible). D6 output signal (TTL compatible). D7 (MSB) output signal (TTL compatible). Output supply pin. Clock input pin. 23 VIN- 18 (12) 19 (13) 20 (14) 21 (14) 22 VDDA VIN+ GNDA GNDA VIN-BIAS 17 PIN NAME 13 (9,11) VDDD 14 (12) 15 (12) 16 VDDA VDDA DESCRIPTION Digital supply pin. Analog supply pin. Analog supply pin.
VREFOUT Full scale reference output. Connect to pin 17 for self bias. (VRTS on 1175) (ML401-1 only) VREFIN Full scale reference input. Connect to pin 16 for self bias. (VRT on 1175) (ML401-1 only) Analog supply pin. Input signal. Analog ground. Analog ground. Common mode bias output. Connect to pin 23 for self bias. (VRBS on 1175) (ML401-1 only) Common mode bias input. Connect to pin 22 for self bias. Drive with the negative input if differential input is being used. (VRB on 1175) (ML401-1 only) Digital Ground.
10 (8) 11 12 (10)
24 (15)
GNDD
2
ML6401
ABSOLUTE MAXIMUM RATINGS
Absolute maximum ratings are those values beyond which the device could be permanently damaged. Absolute maximum ratings are stress ratings only and functional device operation is not implied. Supply Current (ICC) ............................................... 55mA Peak Driver Output Current ............................... 500mA Analog Inputs ................................................... -0.3 to 7V Junction Temperature ............................................. 150C Storage Temperature Range ..................... -65C to 150C Lead Temperature (soldering, 10 sec) ..................... 150C Thermal Resistance (JA) Plastic DIP ....................................................... 80C/W Plastic SOIC ................................................... 110C/W
OPERATING CONDITIONS
Temperature Range ....................................... 0C to 70C TPWH(min) = TPWL(min) ............................................... 25ns
ELECTRICAL CHARACTERISTICS
PARAMETER Resolution Power Dissipation Transfer Function DC Integral Linearity DC Differential Linearity AC Integral Linearity Offset Voltage Gain Error Analog Signal Processing Differential Gain Differential Phase Signal to Noise Ratio Distortion Spurious Free Dynamic Range SIN and Distortion (SINAD) Effective Bits Analog Inputs Input Voltage
Unless otherwise specified, CL = 15pF, VCC = 5V 10%, TA = Operating Temperature Range (Note 1).
CONDITIONS MIN TYP 8 200 325 MAX UNITS Bits mW
fCLk = 15MSPS fCLk = 15MSPS VIN = 2V, 4.4MHz VIN- = VIN-BIAS, VREFOUT = VREFIN VIN- = VIN-BIAS, VREFOUT = VREFIN
0.8 0.6
1.25 1 2 10
LSB LSB LSB LSB LSB
2
5
VIN = NTSC 40 IRE modulated ramp, fCLK = 14.3 MSPS VIN = NTSC 40 IRE modulated ramp, fCLK = 14.3 MSPS VIN = 2V, 1MHz, fCLK = 20MHz
1.8 0.9 48 0.18 58 47 7.4
% degree dB % dB dB bits
Digital Output = 0, VIN- = VIN-BIAS, VREFOUT = VREFIN Digital Output = 255, VIN- = VIN-BIAS, VREFOUT = VREFIN
0.5 2.5 20 4.0 150 30
V V A pF MHz
Input Current Input Capacitance Analog Input Bandwidth Reference Outputs VIN-BIAS VREFOUT VRIN
fCLK = 20MHz VIN = 2V
1.45 IREFOUT = 50A 0.97
1.5 1.0
1.55 1.03 5
V V A
3
ML6401
ELECTRICAL CHARACTERISTICS (Continued)
PARAMETER Switching Characteristics Maximum CLK Input Frequency Clock Duty Cycle tPWH tPWL Analog To Digital Converter Inputs -- CLK Low Level Input Voltage High Level Input Voltage Low Level Input Current High Level Input Current Input Capacitance Timing -- Digital Outputs (CL = 15pF, IOL = 2mA, RL = 2k, fCLK = 20MHz) Sampling Delay Output Hold Time Output Delay Time Three-State Delay Time -- Output Enable Three-State Delay Time -- Output Disable Analog To Digital Converter Outputs -- Digital Low Level Output Voltage High Level Output Voltage Output Current in Three-State Mode Supplies Analog, Digital & Output Supply Voltage Analog Supply Current Digital Supply Current Output Supply Current Static fCLK = 20MHz fCLK = 20MHz, CL = 0pF 4.5 26 10 4 5.5 34 15 10 V mA mA mA IOL = 2mA IOH = 2mA 0 2.4 -20 0.6 VCCO +20 V V A tDS tHO tDO 4 5 5 12 18 10 10 10 30 25 20 ns ns ns ns ns VIL VIH VIL = 0.1V VIH = VDDD - 0.1V 0 2.4 -5 -5 4.0 0.8 VDDD +5 +5 V V A A pF CLK = 13.5MHz CLK 20MHz CLK 20MHz 20 40 25 25 25 60 MHz % ns ns CONDITIONS MIN TYP MAX UNITS
Note 1: Limits are guaranteed by 100% testing, sampling, or correlation with worst-case test conditions.
TIMING DIAGRAM
SAMPLE (VIN+) - (VIN-) N+1
N+2
N+3
N N+4
tDS CLK
N-3
N-2 tHO
N-1
N tPWH OUT
N+1 tPWL
D0 TO D7
tDO
4
ML6401
FUNCTIONAL DESCRIPTION
INTRODUCTION The Micro Linear ML6401 is a single-chip video A/D converter IC which is intended for analog to digital conversion of 2Vp-p signals at rates up to 20MSPS. Incorporating both bias and clock generation, it forms a complete solution for data conversion. The operating power dissipation is typically less than 200mW. The IC is designed to offer low power dissipation and a high level of integration resulting in an optimized solution. The IC consists of an input track and hold, a three stage pipelined A/D converter, digital error correction circuitry, internal dual non-overlapping clock generator, and internal voltage reference. INPUT TRACK AND HOLD The input track and hold consists of a differential capacitor feedback amplifier. The input capacitance, including pin protection and transmission gate, is 4pF. The input to the track and hold can be driven differentially, or single-ended. Single-ended operation uses an internal or external reference to bias the negative input. The full scale range can be set externally, or supplied from an internal source. The track and hold samples the input signal during the positive half cycle of the input clock, and holds the last value of VIN during the negative half cycle of the input clock. The settling time of the amplifier is less than 20ns.
8
A/D CONVERTER The A/D conversion is performed via a three stage pipelined architecture. The first two stages quantize their input signal to three bits, then subtract the result from the input and amplify the difference by a factor of four. This creates a residue signal which spans the full scale range of the following converter. The subtraction and amplification is performed via a differential capacitor feedback amplifier, similar to the input track and hold. The third stage quantizes the signal to four bits. One bit from each of the last two stages is used for error correction. The first stage A/D performs the conversion at the end of the track and hold period, approximately one-half cycle after the input was sampled. The second stage A/D performs the conversion one half cycle later, after the subtraction/amplification of the first stage has settled. The third stage A/D performs the conversion after another onehalf cycle delay, when the second stage has settled. Error correction is then performed, and, one clock cycle later, data is transferred to the output latch. This permits the data to be read 3 clocks after the sample was taken. This technique results in lower input capacitance, lower harmonic distortion, and higher signal to noise ratios than the classical two step parallel technique, providing a greater number of effective bits. CLOCK GENERATION The ML6401 typically requires an input clock that if running at 20MHz would have a low time of 25ns, and a high time of 25ns. This input is applied to a clock generation circuit which creates the two non-overlapping clock signals required by the feedback amplifiers. Pipeline delay is the number of clock cycles between conversion initiation and the associated output data being made available. New output data is provided every clock cycle.
EFB
7
6 1 2 3 4 5 6 FREQUENCY 7 8 9 10
Typical Effective Bits versus Input Signal Frequency.
5
ML6401
INPUT COUPLING The following two figures illustrate two simple means of connecting AC and DC coupled signals into the ML6401-1. CXD1175 REPLACEMENT The 24-pin ML6401-1 is pin compatible with the Sony CXD1175 since all features common to both A/D's share common pins. The 24-pin ML6401-1 is not, however, a direct replacement for the CXD1175. The architectural differences between the two parts result in slightly different application circuits only in the area of the reference pins. The 1175 brings the top and bottom of the reference ladder to external pins (denoted VRT and VRB respectively), and provides two additional pins (VRTS and VRBS) which can be used to bias the ladder. There are three major differences in the use of the 24-pin ML64011. First, there is no single resistor ladder which can be brought out to users in order to vary gain and offset. Second, the 24-pin ML6401 cannot handle full scale ranges of VDDA volts. And third, where the 1175 architecture has two voltages (VRT and VRB) which fix the two endpoints of the conversion range (code 255 and code 0), the 24-pin ML6401 has one voltage (VREF) which affects only full scale range (code 255 - code 0) and one voltage (VIN-) which affects only bias (code 128). An internally generated VREFOUT (1 volt) is brought to pin 16 (VRTS of 1175), and an internally generated VIN-BIAS (1.5 volts) is brought to pin 22 (VRBS of 1175). This allows the following four modes of operation: 1. CXD1175 -- See Figure 3. Connect VRTS to VRT and VRBS to VRB. The ladder will have 2 volts across it (equal to the full scale range), which varies with supply. ML6401 -- With pin 16 connected to pin 17, and pin 22 connected to pin 23, the A/D will supply internally generated bandgap biases, making full scale range 2 volts and bias (code 128) 1.5 volts. This is a virtual drop in for an 1175 with pins 16 and 17 shorted, and pins 22 and 23 shorted (0.1 volt bias difference). 2. CXD1175 -- See Figure 4. Leave VRTS and VRBS open, and drive VRT and VRB with external voltages. The 1175 spec allows VRT-VRB to equal from 1.8 volts to VDDA volts. This allows users the flexibility to supply higher quality references (higher precision, lower noise), and change the full scale range of the A/D (these voltages can be varied to effectively implement a VGA). Also, the offset of the A/D can be varied. ML6401 -- Leave pin 16 and pin 22 open, and drive pin 17 and pin 23 with external voltages. The full scale range will be 2 x pin 17 volts, and the bias (code 128) will occur at pin 23 2% volts. The full scale range of the A/D must be kept below 4 volts, but the part is only specified for full scale range of 2 volts.
VIDEO INPUT + 47F VIN- 0.1F RL 75 0.01F RB 1k RB 1k VIN+ S&H
VIDEO INPUT VDDA -0.5V to +0.5V RA ADC 1 + VDDA VIN+ S&H 3 x RA VIN- ADC 1
+0.5V to 2.5V
RA
RA
10F +
VIN-BIAS 1.5V VREFOUT VREFIN INTERNAL 1.0V REFERENCES RA = 1k TYP 0.01F VIN-BIAS 1.5V VREFOUT VREFIN 0.01F GNDD INTERNAL 1.0V REFERENCES
GNDD
Figure 1. AC Coupled Input, External Resistors Bias the Input.
Figure 2. DC Coupled Input.
6
ML6401
+12V C6 47F + C5 0.1F R3 500 Q2 Q1 + C2 10F R2 180 + R4 1k R5 2k R7* 5k POT R9 5k C8 0.1F C3 + 47F C4 0.1F C12 0.1F *POT R7 WILL HAVE TO BE ADJUSTED Note: Circuit in dashed lines is an optional 1175 input network which can be replaced with circuits in Figure 1 or 2. C7 47F C13 10pF R10 75 13 14 15 16 17 18 19 20 21 22 + C11 0.1F 23 24 R8 100 Q3 C9 + 47F C10 0.1F CLOCK IN +5V HC04
1175 PINOUT
VDDD VDDA VDDA VRTS VRT VDDA VIN+ GNDA GNDA VRBS VRB GNDD CLK VDDO D7 D6 D5 D4 D3 D2 D1 D0 GNDO OE 12 11 10 9 8 7 6 5 4 3 2 1 LSB MSB CLK
C1 470F VIN
R1 120
-12V
Figure 3. Replacement for 1175. 3. CXD1175 -- Connect VRBS to VRB and leave VRTS open while driving VRT with an external voltage. This allows similar functionality to #2 preceding, but the bias voltage (code 0) will move when the full scale range is changed. ML6401 -- Open pin 16, drive pin 17 externally, and connect pin 22 to pin 23. The full scale range will be 2 x pin 17 volts, and the bias (code 128) will occur at 1.5 volts (internally generated from bandgap). The full scale range of the A/D must be kept below 4 volts, but the part is only specified for full scale range of 2 volts. 4. CXD1175 -- Connect VRTS to VRT and leave VRBS open while driving VRB with an external voltage. This allows similar functionality to #2 preceding, but the bias voltage (code 0) will move when the full scale range is changed. ML6401 -- Connect pin 16 to pin 17, open pin 22 and drive pin 23 externally. The full scale range will be 2 volts (internally generated from bandgap), and the bias (code 128) will occur at pin 23 2% volts.
7
ML6401
R12 1k (1) Sony: A to C, B to D (2) Micro Linear: A to D, B to C R13 500
C
R11 1k (1) (2)
PC254 + A - Q4
D
(2) (1)
B
- + PC254
Q5
+12V C6 47F + C5 0.1F R3 500 Q2 Q1 + C2 10F R2 180 + R4 1k R5 2k R7* 5k POT R9 5k C8 0.1F C3 + 47F C4 0.1F C12 0.1F *POT R7 WILL HAVE TO BE ADJUSTED
Note: Circuit in dashed lines is an optional 1175 input network which can be replaced with circuits in Figure 1 or 2.
HC04 CLOCK IN R8 100 Q3 13 14 R10 75 15 16 17 18 19 C13 10pF 20 21 22 + C7 47F C11 0.1F 23 24 C9 + 47F C10 0.1F +5V
1175 PINOUT
VDDD VDDA VDDA VRTS VRT VDDA VIN+ GNDA GNDA VRBS VRB GNDD CLK VDDO D7 D6 D5 D4 D3 D2 D1 D0 GNDO OE 12 11 10 9 8 7 6 5 4 3 2 1 LSB MSB CLK
C1 470F VIN
R1 120
-12V
Figure 4. Replacement with Wiring Changes (shown) for the 1175.
8
ML6401
PHYSICAL DIMENSIONS inches (millimeters)
Package: S24 24-Pin SOIC
0.600 - 0.614 (15.24 - 15.60) 24
0.291 - 0.301 0.398 - 0.412 (7.39 - 7.65) (10.11 - 10.47) PIN 1 ID
1 0.024 - 0.034 (0.61 - 0.86) (4 PLACES) 0.050 BSC (1.27 BSC) 0.095 - 0.107 (2.41 - 2.72) 0 - 8
0.090 - 0.094 (2.28 - 2.39)
0.012 - 0.020 (0.30 - 0.51)
SEATING PLANE
0.005 - 0.013 (0.13 - 0.33)
0.022 - 0.042 (0.56 - 1.07)
0.009 - 0.013 (0.22 - 0.33)
Package: S16N 16-Pin Narrow SOIC
0.386 - 0.396 (9.80 - 10.06) 16
PIN 1 ID
0.148 - 0.158 0.228 - 0.244 (3.76 - 4.01) (5.79 - 6.20)
1 0.017 - 0.027 (0.43 - 0.69) (4 PLACES) 0.050 BSC (1.27 BSC) 0.059 - 0.069 (1.49 - 1.75) 0 - 8
0.055 - 0.061 (1.40 - 1.55)
0.012 - 0.020 (0.30 - 0.51)
SEATING PLANE
0.004 - 0.010 (0.10 - 0.26)
0.015 - 0.035 (0.38 - 0.89)
0.006 - 0.010 (0.15 - 0.26)
11
ML6401
ORDERING INFORMATION
PART NUMBER ML6401CS-1 ML6401CS-3 TEMPERATURE RANGE 0C to 70C 0C to 70C PACKAGE 24-Pin SOIC (S24) 16-Pin SOIC (S16N) (EOL)
(c) Micro Linear 1997 is a registered trademark of Micro Linear Corporation Products described in this document may be covered by one or more of the following patents, U.S.: 4,897,611; 4,964,026; 5,027,116; 5,281,862; 5,283,483; 5,418,502; 5,508,570; 5,510,727; 5,523,940; 5,546,017; 5,559,470; 5,565,761; 5,592,128; 5,594,376; Japan: 2598946. Other patents are pending.
Micro Linear reserves the right to make changes to any product herein to improve reliability, function or design. Micro Linear does not assume any liability arising out of the application or use of any product described herein, neither does it convey any license under its patent right nor the rights of others. The circuits contained in this data sheet are offered as possible applications only. Micro Linear makes no warranties or representations as to whether the illustrated circuits infringe any intellectual property rights of others, and will accept no responsibility or liability for use of any application herein. The customer is urged to consult with appropriate legal counsel before deciding on a particular application.
2092 Concourse Drive San Jose, CA 95131 Tel: 408/433-5200 Fax: 408/432-0295
DS6401-01
10

▲Up To Search▲

Price & Availability of ML6401CS-3

	To Download ML6401CS-3 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .